diff -r -u linux-2.2.10/Documentation/Configure.help linux/Documentation/Configure.help --- linux-2.2.10/Documentation/Configure.help Sun Jun 13 22:54:06 1999 +++ linux/Documentation/Configure.help Fri Jul 9 10:14:28 1999 @@ -1328,6 +1328,12 @@ say N here to save some memory. You can also say Y if you have an "intelligent" multiport card such as Cyclades, Digiboards, etc. +Support an additional 128 serial ports +CONFIG_SERIAL_LEGION_PORTS + Say Y here if you need an obscene number of serial ports; if you + notice all your PCI serial ports aren't being configured or you + have an NT 960 for instance. Usually you should say N here. + Support for sharing serial interrupts CONFIG_SERIAL_SHARE_IRQ Some serial boards have hardware support which allows multiple dumb @@ -1350,6 +1356,14 @@ signal when there are any serial ports on the board which need servicing. Say Y here to enable the serial driver to take advantage of those special I/O ports. + +Autodetect PCI serial boards +CONFIG_SERIAL_DETECT_PCI + PCI-based serial boards can be automatically detected and configured + by the serial driver. If you're unsure if your serial board is PCI- + based, say yes. Saying no here will prevent the autodetection (but + manual setup is still okay), and your kernel will be mildly smaller + and boot a little faster. SGI Zilog85C30 serial support CONFIG_SGI_SERIAL diff -r -u linux-2.2.10/drivers/char/Config.in linux/drivers/char/Config.in --- linux-2.2.10/drivers/char/Config.in Fri May 7 14:05:30 1999 +++ linux/drivers/char/Config.in Fri Jul 9 10:18:28 1999 @@ -15,10 +15,12 @@ bool 'Extended dumb serial driver options' CONFIG_SERIAL_EXTENDED if [ "$CONFIG_SERIAL_EXTENDED" = "y" ]; then bool ' Support more than 4 serial ports' CONFIG_SERIAL_MANY_PORTS + bool ' Support an additional 128 serial ports' CONFIG_SERIAL_LEGION_PORTS bool ' Support for sharing serial interrupts' CONFIG_SERIAL_SHARE_IRQ bool ' Autodetect IRQ on standard ports (unsafe)' CONFIG_SERIAL_DETECT_IRQ bool ' Support special multiport boards' CONFIG_SERIAL_MULTIPORT bool ' Support the Bell Technologies HUB6 card' CONFIG_HUB6 + bool ' Autodetect PCI serial boards' CONFIG_SERIAL_DETECT_PCI fi bool 'Non-standard serial port support' CONFIG_SERIAL_NONSTANDARD if [ "$CONFIG_SERIAL_NONSTANDARD" = "y" ]; then diff -r -u linux-2.2.10/drivers/char/serial.c linux/drivers/char/serial.c --- linux-2.2.10/drivers/char/serial.c Tue Mar 23 16:13:58 1999 +++ linux/drivers/char/serial.c Fri Jul 9 12:02:32 1999 @@ -32,6 +32,10 @@ * 4/98: Added changes to support the ARM architecture proposed by * Russell King * + * 5/99: Updated to include support for the XR16C850 and ST16C654 + * uarts and PCI multiport boards. + * Stuart MacDonald + * * This module exports the following rs232 io functions: * * int rs_init(void); @@ -48,6 +52,9 @@ * Enables support for ports beyond the standard, stupid * COM 1/2/3/4. * + * CONFIG_SERIAL_LEGION_PORTS + * Support for 128 additional ports + * * CONFIG_SERIAL_MULTIPORT * Enables support for special multiport board support. * @@ -57,6 +64,9 @@ * CONFIG_SERIAL_DETECT_IRQ * Enable the autodetection of IRQ on standart ports * + * CONFIG_SERIAL_DETECT_PCI + * Enable the autodetection of PCI multiport boards + * * SERIAL_PARANOIA_CHECK * Check the magic number for the async_structure where * ever possible. @@ -70,8 +80,10 @@ /* Normally these defines are controlled by the autoconf.h */ #define CONFIG_SERIAL_MANY_PORTS +#define CONFIG_SERIAL_LEGION_PORTS #define CONFIG_SERIAL_SHARE_IRQ #define CONFIG_SERIAL_DETECT_IRQ +#define CONFIG_SERIAL_DETECT_PCI #define CONFIG_SERIAL_MULTIPORT #define CONFIG_HUB6 #endif @@ -93,6 +105,20 @@ #endif #endif +#ifdef CONFIG_SERIAL_DETECT_PCI +/* Can't detect pci boards without pci bus support */ +#ifndef CONFIG_PCI +#undef CONFIG_SERIAL_DETECT_PCI +#else +#ifndef CONFIG_SERIAL_MANY_PORTS +#define CONFIG_SERIAL_MANY_PORTS +#endif +#ifndef CONFIG_SERIAL_SHARE_IRQ +#define CONFIG_SERIAL_SHARE_IRQ +#endif +#endif /* CONFIG_PCI */ +#endif /* CONFIG_SERIAL_DETECT_PCI */ + /* Set of debugging defines */ #undef SERIAL_DEBUG_INTR @@ -141,6 +167,9 @@ #ifdef CONFIG_SERIAL_CONSOLE #include #endif +#ifdef CONFIG_SERIAL_DETECT_PCI +#include +#endif #include #include @@ -197,7 +226,10 @@ { "ST16650", 1, UART_CLEAR_FIFO | UART_STARTECH }, { "ST16650V2", 32, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH }, + { "ST16654", 64, UART_CLEAR_FIFO | UART_USE_FIFO | + UART_STARTECH }, { "TI16750", 64, UART_CLEAR_FIFO | UART_USE_FIFO}, + { "XR16850", 128, UART_CLEAR_FIFO | UART_STARTECH }, { 0, 0} }; @@ -211,6 +243,16 @@ static struct termios *serial_termios[NR_PORTS]; static struct termios *serial_termios_locked[NR_PORTS]; +#ifdef CONFIG_SERIAL_DETECT_PCI + +static struct pci_board pci_table[] = { + SERIAL_PCI_BOARD_DFNS /* Defined in serial.h */ +}; + +#define NR_PCI_BOARDS (sizeof(pci_table)/sizeof(struct pci_board)) + +#endif + #ifndef MIN #define MIN(a,b) ((a) < (b) ? (a) : (b)) #endif @@ -1375,6 +1417,14 @@ serial_outp(info, UART_LCR, 0xBF); serial_outp(info, UART_EFR, (cflag & CRTSCTS) ? UART_EFR_CTS : 0); + if (info->state->type == PORT_16850) { + serial_outp(info, UART_FCTR, UART_FCTR_TRGD | + UART_FCTR_RX); + serial_outp(info, UART_TRG, UART_TRG_96); + serial_outp(info, UART_FCTR, UART_FCTR_TRGD | + UART_FCTR_TX); + serial_outp(info, UART_TRG, UART_TRG_96); + } } serial_outp(info, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */ serial_outp(info, UART_DLL, quot & 0xff); /* LS of divisor */ @@ -2823,6 +2873,10 @@ printk(" MANY_PORTS"); #define SERIAL_OPT #endif +#ifdef CONFIG_SERIAL_LEGION_PORTS + printk(" LEGION_PORTS"); +#define SERIAL_OPT +#endif #ifdef CONFIG_SERIAL_MULTIPORT printk(" MULTIPORT"); #define SERIAL_OPT @@ -2835,6 +2889,10 @@ printk(" DETECT_IRQ"); #define SERIAL_OPT #endif +#ifdef CONFIG_SERIAL_DETECT_PCI + printk(" DETECT_PCI"); +#define SERIAL_OPT +#endif #ifdef SERIAL_OPT printk(" enabled\n"); #else @@ -2919,8 +2977,12 @@ static void autoconfig(struct serial_state * state) { unsigned char status1, status2, scratch, scratch2; + unsigned char old_fctr, old_emsr, old_fcr, old_mcr; + unsigned char old_dll, old_dlm; + int count; struct async_struct *info, scr_info; unsigned long flags; + unsigned long last_jiff; state->type = PORT_UNKNOWN; @@ -3005,8 +3067,73 @@ state->type = PORT_16650; } else { serial_outp(info, UART_LCR, 0xBF); - if (serial_in(info, UART_EFR) == 0) - state->type = PORT_16650V2; + if (serial_in(info, UART_EFR) == 0) { + old_fctr = serial_inp(info, UART_FCTR); + serial_outp(info, UART_FCTR, old_fctr | + UART_FCTR_SCR_SWAP); + old_emsr = serial_inp(info, UART_EMSR); + serial_outp(info, UART_EMSR, 0x00); + serial_outp(info, UART_LCR, scratch2); + scratch = serial_in(info, UART_SCR); + serial_outp(info, UART_SCR, 0xa5); + status1 = serial_in(info, UART_SCR); + serial_outp(info, UART_SCR, 0x5a); + status2 = serial_in(info, UART_SCR); + serial_outp(info, UART_SCR, scratch); + if ((status1 != 0xa5) || (status2 != 0x5a)) { + serial_outp(info, UART_LCR, 0xBF); + serial_outp(info, UART_FCTR, old_fctr | + UART_FCTR_SCR_SWAP); + serial_outp(info, UART_EMSR, old_emsr); + serial_outp(info, UART_FCTR, old_fctr); + state->type = PORT_16850; + } else { + old_fcr = serial_inp(info, UART_FCR); + old_mcr = serial_inp(info, UART_MCR); + /* + * Since this is a 16650 type uart, the + * attempted write to the 850 FCTR has + * trashed the IER. Restore it here. + */ + serial_outp(info, UART_IER, old_fctr); + serial_outp(info, UART_FCR, + UART_FCR_ENABLE_FIFO | + UART_FCR_CLEAR_RCVR | + UART_FCR_CLEAR_XMIT); + serial_outp(info, UART_MCR, + UART_MCR_LOOP); + serial_outp(info, UART_LCR, + UART_LCR_DLAB); + old_dll = serial_inp(info, UART_DLL); + old_dlm = serial_inp(info, UART_DLM); + serial_outp(info, UART_DLL, 0x01); + serial_outp(info, UART_DLM, 0x00); + serial_outp(info, UART_LCR, 0x03); + for (count = 0; count < 64; count++) + serial_outp(info, UART_TX, + count); + restore_flags(flags); + last_jiff = jiffies; + while (jiffies - last_jiff < 2); + save_flags(flags); cli(); + for (count = 0; (serial_inp(info, + UART_LSR) & + UART_LSR_DR) && + (count < 64); + count++) + serial_inp(info, UART_RX); + serial_outp(info, UART_FCR, old_fcr); + serial_outp(info, UART_MCR, old_mcr); + serial_outp(info, UART_LCR, + UART_LCR_DLAB); + serial_outp(info, UART_DLL, old_dll); + serial_outp(info, UART_DLM, old_dlm); + if (count == 64) + state->type = PORT_16654; + else + state->type = PORT_16650V2; + } + } } } if (state->type == PORT_16550A) { @@ -3070,6 +3197,23 @@ EXPORT_SYMBOL(register_serial); EXPORT_SYMBOL(unregister_serial); +#ifdef CONFIG_SERIAL_DETECT_PCI +/* + * Finds the first rs_table entry that's free (has no flags set) equal + * to or greater than start. + */ +static int next_free_rs_entry(int start) +{ + int i; + + if (start < 0) start = 0; + + for (i = start; (i < NR_PORTS) && rs_table[i].flags; i++); + + return i; +} +#endif + /* * The serial driver boot-time initialization code! */ @@ -3077,6 +3221,13 @@ { int i; struct serial_state * state; +#ifdef CONFIG_SERIAL_DETECT_PCI + int j, k; + struct pci_board *board; + struct pci_dev *device; + unsigned short config; + unsigned char irq; +#endif extern void atomwide_serial_init (void); extern void dualsp_serial_init (void); @@ -3169,6 +3320,55 @@ if (tty_register_driver(&callout_driver)) panic("Couldn't register callout driver\n"); +#ifdef CONFIG_SERIAL_DETECT_PCI + /* + * Just in case someone turns on PCI bus support without having a + * pci bus present + */ + if (pci_present()) { + for (i = 0, j = next_free_rs_entry(0), board = pci_table; + (i < NR_PCI_BOARDS) && (j < NR_PORTS); + i++, board++) { + for (device = pci_find_device(board->vendor, + board->device, NULL); + device && (j < NR_PORTS); + device = pci_find_device(board->vendor, + board->device, device)) { + pci_read_config_word(device, + PCI_SUBSYSTEM_VENDOR_ID, &config); + if (config != board->subvendor) + continue; + pci_read_config_word(device, PCI_SUBSYSTEM_ID, + &config); + if (config != board->subdevice) + continue; + pci_read_config_byte(device, PCI_INTERRUPT_LINE, + &irq); + pci_read_config_word(device, board->uart_reg, + &config); + config &= board->uart_mask; + for (k = 0; (k < board->num_ports) && + (j < NR_PORTS); k++, + j = next_free_rs_entry(j + 1)) { + rs_table[j].baud_base = + board->base_baud; + rs_table[j].port = config + k * 8; + rs_table[j].irq = irq; + /* + * Turning on the autodetect irq is a + * waste because we already know what + * the irq is. STD_COM_FLAGS may have + * it turned on, so don't use that + * define. + */ + rs_table[j].flags = ASYNC_BOOT_AUTOCONF + | ASYNC_SKIP_TEST; + } /* for */ + } /* for */ + } /* for */ + } /* if */ +#endif + for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) { state->magic = SSTATE_MAGIC; state->line = i; diff -r -u linux-2.2.10/include/asm-i386/serial.h linux/include/asm-i386/serial.h --- linux-2.2.10/include/asm-i386/serial.h Tue May 11 13:35:45 1999 +++ linux/include/asm-i386/serial.h Fri Jul 9 11:10:10 1999 @@ -3,6 +3,7 @@ */ #include +#include /* * This assumes you have a 1.8432 MHz clock for your UART. @@ -120,9 +121,237 @@ #define MCA_SERIAL_PORT_DFNS #endif +#ifdef CONFIG_SERIAL_LEGION_PORTS +#define LEGION_SERIAL_PORT_DEFNS \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, \ + { 0, BASE_BAUD, 0x000, 0, 0 }, +#else +#define LEGION_SERIAL_PORT_DEFNS +#endif + #define SERIAL_PORT_DFNS \ STD_SERIAL_PORT_DEFNS \ EXTRA_SERIAL_PORT_DEFNS \ HUB6_SERIAL_PORT_DFNS \ - MCA_SERIAL_PORT_DFNS + MCA_SERIAL_PORT_DFNS \ + LEGION_SERIAL_PORT_DEFNS +#ifdef CONFIG_SERIAL_DETECT_PCI + +#define SERIAL_PCI_BOARD_DFNS \ + /* Vendor ID */ \ + /* Device ID */ \ + /* Subvendor ID */ \ + /* Subdevice ID */ \ + /* Number of Ports */ \ + /* Base (Maximum) Baud Rate */ \ + /* Offset of register holding Uart register offset */ \ + /* Mask to apply to above register's value */ \ + { PCI_VENDOR_ID_V3, \ + PCI_DEVICE_ID_V3_V960, \ + PCI_SUBVENDOR_ID_CONNECT_TECH, \ + PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, \ + 8, 1382400, PCI_BASE_ADDRESS_1, 0xfffc }, \ + { PCI_VENDOR_ID_V3, \ + PCI_DEVICE_ID_V3_V960, \ + PCI_SUBVENDOR_ID_CONNECT_TECH, \ + PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, \ + 4, 1382400, PCI_BASE_ADDRESS_1, 0xfffc }, \ + { PCI_VENDOR_ID_V3, \ + PCI_DEVICE_ID_V3_V960, \ + PCI_SUBVENDOR_ID_CONNECT_TECH, \ + PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, \ + 2, 1382400, PCI_BASE_ADDRESS_1, 0xfffc }, \ + { PCI_VENDOR_ID_V3, \ + PCI_DEVICE_ID_V3_V960V2, \ + PCI_SUBVENDOR_ID_CONNECT_TECH, \ + PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, \ + 8, 1382400, PCI_BASE_ADDRESS_1, 0xfffc }, \ + { PCI_VENDOR_ID_V3, \ + PCI_DEVICE_ID_V3_V960V2, \ + PCI_SUBVENDOR_ID_CONNECT_TECH, \ + PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, \ + 4, 1382400, PCI_BASE_ADDRESS_1, 0xfffc }, \ + { PCI_VENDOR_ID_V3, \ + PCI_DEVICE_ID_V3_V960V2, \ + PCI_SUBVENDOR_ID_CONNECT_TECH, \ + PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, \ + 2, 1382400, PCI_BASE_ADDRESS_1, 0xfffc }, \ + { PCI_VENDOR_ID_V3, \ + PCI_DEVICE_ID_V3_V960, \ + PCI_SUBVENDOR_ID_CONNECT_TECH, \ + PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, \ + 8, 921600, PCI_BASE_ADDRESS_1, 0xfffc }, \ + { PCI_VENDOR_ID_V3, \ + PCI_DEVICE_ID_V3_V960, \ + PCI_SUBVENDOR_ID_CONNECT_TECH, \ + PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, \ + 8, 921600, PCI_BASE_ADDRESS_1, 0xfffc }, \ + { PCI_VENDOR_ID_V3, \ + PCI_DEVICE_ID_V3_V960, \ + PCI_SUBVENDOR_ID_CONNECT_TECH, \ + PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, \ + 4, 921600, PCI_BASE_ADDRESS_1, 0xfffc }, \ + { PCI_VENDOR_ID_V3, \ + PCI_DEVICE_ID_V3_V960, \ + PCI_SUBVENDOR_ID_CONNECT_TECH, \ + PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, \ + 4, 921600, PCI_BASE_ADDRESS_1, 0xfffc }, \ + { PCI_VENDOR_ID_V3, \ + PCI_DEVICE_ID_V3_V960, \ + PCI_SUBVENDOR_ID_CONNECT_TECH, \ + PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, \ + 2, 921600, PCI_BASE_ADDRESS_1, 0xfffc }, \ + { PCI_VENDOR_ID_V3, \ + PCI_DEVICE_ID_V3_V960V2, \ + PCI_SUBVENDOR_ID_CONNECT_TECH, \ + PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, \ + 8, 921600, PCI_BASE_ADDRESS_1, 0xfffc }, \ + { PCI_VENDOR_ID_V3, \ + PCI_DEVICE_ID_V3_V960V2, \ + PCI_SUBVENDOR_ID_CONNECT_TECH, \ + PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, \ + 8, 921600, PCI_BASE_ADDRESS_1, 0xfffc }, \ + { PCI_VENDOR_ID_V3, \ + PCI_DEVICE_ID_V3_V960V2, \ + PCI_SUBVENDOR_ID_CONNECT_TECH, \ + PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, \ + 4, 921600, PCI_BASE_ADDRESS_1, 0xfffc }, \ + { PCI_VENDOR_ID_V3, \ + PCI_DEVICE_ID_V3_V960V2, \ + PCI_SUBVENDOR_ID_CONNECT_TECH, \ + PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, \ + 4, 921600, PCI_BASE_ADDRESS_1, 0xfffc }, \ + { PCI_VENDOR_ID_V3, \ + PCI_DEVICE_ID_V3_V960V2, \ + PCI_SUBVENDOR_ID_CONNECT_TECH, \ + PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, \ + 2, 921600, PCI_BASE_ADDRESS_1, 0xfffc }, + +#endif diff -r -u linux-2.2.10/include/linux/pci.h linux/include/linux/pci.h --- linux-2.2.10/include/linux/pci.h Wed Jun 9 19:59:34 1999 +++ linux/include/linux/pci.h Fri Jul 9 11:09:35 1999 @@ -864,6 +864,12 @@ #define PCI_VENDOR_ID_LITEON 0x11ad #define PCI_DEVICE_ID_LITEON_LNE100TX 0x0002 +#define PCI_VENDOR_ID_V3 0x11b0 +#define PCI_DEVICE_ID_V3_V960 0x0001 +#define PCI_DEVICE_ID_V3_V350 0x0001 +#define PCI_DEVICE_ID_V3_V960V2 0x0002 +#define PCI_DEVICE_ID_V3_V350V2 0x0002 + #define PCI_VENDOR_ID_NP 0x11bc #define PCI_DEVICE_ID_NP_PCI_FDDI 0x0001 @@ -1119,6 +1125,22 @@ #define PCI_DEVICE_ID_ARK_STING 0xa091 #define PCI_DEVICE_ID_ARK_STINGARK 0xa099 #define PCI_DEVICE_ID_ARK_2000MT 0xa0a1 + +/* + * SubVendor and card ID's: sort these numerically according to vendor + * (and according to card ID within vendor). Send all updates to + * . + */ + +#define PCI_SUBVENDOR_ID_CONNECT_TECH 0x12c4 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232 0x0001 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232 0x0002 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232 0x0003 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485 0x0004 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4 0x0005 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485 0x0006 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2 0x0007 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485 0x0008 /* * The PCI interface treats multi-function devices as independent diff -r -u linux-2.2.10/include/linux/serial.h linux/include/linux/serial.h --- linux-2.2.10/include/linux/serial.h Wed Nov 4 01:05:25 1998 +++ linux/include/linux/serial.h Fri Jul 9 10:32:33 1999 @@ -45,9 +45,11 @@ #define PORT_CIRRUS 5 /* usurped by cyclades.c */ #define PORT_16650 6 #define PORT_16650V2 7 -#define PORT_16750 8 -#define PORT_STARTECH 9 /* usurped by cyclades.c */ -#define PORT_MAX 9 +#define PORT_16654 8 +#define PORT_16750 9 +#define PORT_16850 10 +#define PORT_STARTECH 11 /* usurped by cyclades.c */ +#define PORT_MAX 11 struct serial_uart_config { char *name; @@ -139,4 +141,16 @@ extern void unregister_serial(int line); #endif /* __KERNEL__ */ + +struct pci_board { + unsigned short vendor; + unsigned short device; + unsigned short subvendor; + unsigned short subdevice; + int num_ports; + int base_baud; + unsigned char uart_reg; + unsigned short uart_mask; +}; + #endif /* _LINUX_SERIAL_H */ diff -r -u linux-2.2.10/include/linux/serial_reg.h linux/include/linux/serial_reg.h --- linux-2.2.10/include/linux/serial_reg.h Mon May 25 13:32:52 1998 +++ linux/include/linux/serial_reg.h Fri Jul 9 10:34:54 1999 @@ -17,8 +17,14 @@ #define UART_RX 0 /* In: Receive buffer (DLAB=0) */ #define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ #define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ +#define UART_TRG 0 /* (LCR=BF) FCTR bit 7 selects Rx or Tx + * In: Fifo count + * Out: Fifo custom trigger levels */ + /* XR16C85x only */ #define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */ #define UART_IER 1 /* Out: Interrupt Enable Register */ +#define UART_FCTR 1 /* (LCR=BF) Feature Control Register */ + /* XR16C85x only */ #define UART_IIR 2 /* In: Interrupt ID Register */ #define UART_FCR 2 /* Out: FIFO Control Register */ #define UART_EFR 2 /* I/O: Extended Features Register */ @@ -28,6 +34,9 @@ #define UART_LSR 5 /* In: Line Status Register */ #define UART_MSR 6 /* In: Modem Status Register */ #define UART_SCR 7 /* I/O: Scratch Register */ +#define UART_EMSR 7 /* (LCR=BF) Extended Mode Select Register */ + /* FCTR bit 6 selects SCR or EMSR */ + /* XR16c85x only */ /* * These are the definitions for the FIFO Control Register @@ -139,6 +148,45 @@ /* * the low four bits control software flow control */ + +/* + * These are the definitions for the Feature Control Register + * (XR16C85x only, when LCR=bf) + */ +#define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */ +#define UART_FCTR_RTS_4DELAY 0x01 +#define UART_FCTR_RTS_6DELAY 0x02 +#define UART_FCTR_RTS_8DELAY 0x03 +#define UART_FCTR_IRDA 0x04 /* IrDa data encode select */ +#define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */ +#define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */ +#define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */ +#define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */ +#define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */ +#define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */ +#define UART_FCTR_RX 0x00 /* Programmable trigger mode select */ +#define UART_FCTR_TX 0x80 /* Programmable trigger mode select */ + +/* + * These are the definitions for the Enhanced Mode Select Register + * (XR16C85x only, when LCR=bf and FCTR bit 6=1) + */ +#define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */ +#define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */ + +/* + * These are the definitions for the Programmable Trigger + * Register (XR16C85x only, when LCR=bf) + */ +#define UART_TRG_1 0x01 +#define UART_TRG_4 0x04 +#define UART_TRG_8 0x08 +#define UART_TRG_16 0x10 +#define UART_TRG_32 0x20 +#define UART_TRG_64 0x40 +#define UART_TRG_96 0x60 +#define UART_TRG_120 0x78 +#define UART_TRG_128 0x80 #endif /* _LINUX_SERIAL_REG_H */